An integrated dynamic memory in the form of a DRAM generally has a memory cell array, which comprises word lines and bit lines. In this context, the memory cells are arranged at crossover points between the bit lines and word lines. For example, the memory cells are constructed from a storage capacitor and a selection transistor, with the selection transistor connecting the respective storage capacitor to one of the bit lines. Control connections on the respective selection transistors are respectively connected to one of the word lines in order to select the memory cells. An activated word line respectively turns on connected selection transistors. Following selection of a word line, the bit lines in question carry data signals associated with the memory cells along the selected word line. A data signal associated with a selected memory cell is assessed and amplified in a sense amplifier in the memory cell array. During read access the data signals associated with selected memory cells are read for the purpose of further processing, and during write access data signals which are to be written are written to the selected memory cells.
In integrated dynamic memories in the form of DRAMs, a “refresh mode” is required at operating times at which no external access to memory cells is taking place, in order to refresh and thus permanently retain the memory cell content, which may disappear as a result of leakage currents in the storage capacitor or selection transistor, for example. In refresh mode, the assessed and amplified data signals from selected memory cells are written back directly to the memory cells in question. This is generally controlled by a control circuit which also stipulates a refresh rate at which the memory cell content is respectively refreshed.
Particularly for DRAM memory chips, the user generally demands ever higher operating temperatures. In this context, however, it should be noted that the data retention time of the memory cells decreases as the operating temperature increases, since the storage capacitor's and/or the respective selection transistor's leakage currents arising in the memory cells increase as operating temperatures rise. In this case, the refresh rate can be chosen to be lower the longer the maximum attainable data retention time of a memory cell, and hence, the possible period between two refresh cycles for this memory cell. To date, the described temperature response of the data retention time specifies a common maximum operating temperature, and hence a defined refresh rate, generally for all DRAM memory chips of one type, which means that excessive restrictions on memory access on account of pauses in memory access which are induced by the refresh mode are thus avoided.